Express by a truth table, the output Y for all possible input A and B in the following circuit Fig.
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The circuit and truth table are shown in Fig. & . `|("A B",Y'=(A.B),Y=(A+(A.B))),("0 0",0,0),("1 0",0,1),("0 1",0,0),("1 1",1,1)|` Explanation The output of gate I is `y^(')=A.B` The output of gate II is `y=A+(A.B)`
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