Input A and B are applied to the logic gate set up as shown in Fig.Complete the truth table given below and name the equivalent gate formed by this set up.

Explanation

The Boolean expressions for the upper and lower
NOT gates will be, `A^(')=barA` and `B^(')=barB`.
Output of middle OR gate is
`y^(')=A^(')+B^(')=barA+barB`
Output of last NOT gate is
`y=bar(y^('))=bar(barA+barB)`
`=bar(barA).bar(barB)=A.B`
It means the circuit is equivalent to AND gate. The complete truth table is shown below.
`|{:(A,B,A'=barA,B'=barB,y=A.B),(0,0,1,1,0),(0,1,1,0,0),(1,0,0,1,0),(1,1,0,0,1):}|`