Write the truth table for the circuit shown in Fig.
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The output of gate I (i.e., AND gate) is `y_(1)=A.barB` The output of gate II (i.e., AND gate) is `y_(2)=barA.B` The output of gate III (i.e., OR gate) is `y=y_(1)+y_(2)=A.barB+barA.B` The truth table is shown below `|{:(A,B,barA,barB,A.barB,bar.B,y=A.barB+barA.B),(0,0,1,1,0,0,0),(0,1,1,0,0,1,1),(1,0,0,1,1,0,1),(1,1,0,0,0,0,0):}|`
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