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The circuit diagram (see fig.) shows a '...

The circuit diagram (see fig.) shows a 'logic combination' with the states outputs `X,Y` and `Z` given for input `P,Q,R` and `S` all at state `1` (i.e., high). When inputs `P` and `R` change to state `0` i.e., low) with inputs `Q` and `S` still at `1`, the condition of output `X,Y` and `Z` chages to

A

`1,0,0`

B

`1,1,1`

C

`0,1,0`

D

`0,0,1`

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