Sketch the output Y from a NAND gate having inputs A and B given below .

Explanation

For `t le t_(1), " " A = 1 , B = 1 ,` Hence Y = 0
For `t_(1)` to `t_(2), " " A = 0 , B = 0 ,` Hence Y = 1
For `t_(2)` to `t_(3), " " A = 0 , B = 1` , Hence Y = 1
For `t_(3)` to `t_(4) , " " A = 1 , B = 0,` Hence Y = 1
For `t_(4)` to `t_(5), " " A = 1 , B = 1`, Hence Y = 0
For `t_(5)` to `t_(6), " " A = 0 , B = 0` , Hence Y = 1
For `t gt t_(6) , " " A = 0 , B = 1` , Hence Y = 1