Draw the truth table for the logic gate arrangement shown in the figure.

Answer

`(##RES_SCEWCS_PHY_XII_C01_E01_167_A01##)`

Explanation

`{:(,"Input",,"output"),(A,B,,Y=A+B),(0,0,,0),(0,1,,1),(1,1,,1):}`
From the logic gate circuit
`Y=overlineoverline(A.B)`
By de morgan's theorem
`overline(A+B)=overline(A.B)`
So, `Y=overlineoverline(A+B)`
or `Y=A+B`
This is Boolean expression of OR gate whose truth table is given below: