The circuit is equivalent to

Options

A. AND gate
B. NAND gate
C. NOR gate
D. OR gate

Answer

C

Explanation

The gate circuit can be shown by giving two inputs A and B.

Output of NOR gate `Y_(1)=overline(A+B)`
Output NAND gate, `Y_(2)=overline(Y_(1).Y_(2))`
`=overline(Y_(1))+overline(Y_(1))`
`=overlineoverline(A+B)+overlineoverline(A+B)`
`=(A+B)+(A+B)`
`=A+B`
Out of NOT gate `Y=overline(Y_(2))`
`=overline(A+B)`
Which is the output of NOR gate. Alternative:

`{:(" ""NOR",,"NAND",,"NOT",),("A B Y"_(1),Y_(1),Y_(1),Y_(2),Y,),("0 0 1",1,1,0,1,),("0 1 0",0,0,1,0,),("1 0 0",0,0,1,0,),("1 1 0",0,0,1,0,):}`
Same as NOR gate
`{:(" ""NOR Gate"),("0 0 1"),("0 1 0"),("1 0 0"),("1 1 0"):}`.