The diagram of a logic circuit is given below . The output F of the circuit is represented by :

Options

A. `W.(X+Y)`
B. `W.(X.Y)`
C. `W+(X.Y)`
D. `W+(X+Y)`

Answer

C

Explanation

Output of upper OR gate = W + X
Output of lower OR gate = W + Y
Net output F = (W+X) (W+Y)
`="WW" +WY + "XW" + "XY "` [Since WW = W]
`=W(1+Y)+XW+XY" "` [Since 1 + Y =1 ]
`=W +XW +XY = W(1+X)+XY=W+XY`